The testing of integrated circuits has evolved into a highly developed area of technology. Testing may be performed by external equipment, by Built-In Self-Test (BIST) circuitry or by a combination of the two. Generally, all test methods involve shifting data into scannable memory elements in an integrated circuits, capturing the input to the memory elements, shifting the captured data out and then comparing the captured data with predetermined values to determine whether the circuit has performed according to design. As advanced as this field has become, integrated circuits are becoming increasingly more complex and operate at increasingly higher speeds. This has created new problems which existing test methods cannot handle effectively. One problem of particular concern are the effects of clock skew, mis-alignment of clock signals between clock domains, when signals are exchanged between different clock domains in the circuit at high test clock speeds. Clearly, invalid test results would be obtained when a signal originating from a component in one clock domain arrives in a destination component in another clock domain too soon or too late. Thus, measures must be taken to re-time or synchronize the clocks of different clock domains.
Existing re-timing techniques are satisfactory for testing circuits at low speed. However, new testing techniques are required to handle clock skew that is significantly larger than one half of the highest frequency of the circuit for high speed testing.
Several techniques have been proposed for eliminating timing problems between clock domains during scan and scan-based BIST. One method, used in commercial tools, scans in test vectors (test data) into and performs a capture operation on only one clock domain at a time or only on clock domains that do not interact with one another. This eliminates hold problems resulting from a Flip-Flop capturing early such that the result of the capture operation has time to propagate during the same clock cycle to another Flip-Flop located in a different clock domain. The method requires longer test times because only a fraction of the Flip-Flops in the design can capture at any one time. This method cannot be used easily for high-speed testing because it does not provide a mechanism to prevent setup time violation for high-frequency data signals being captured in a different clock domain.
Another method uses Flip-Flops or transparent latches to re-time data signals crossing frequency domain boundaries. This method eliminates hold problems at low frequency and reduces test time since all Flip-Flops capture at the same time. However, the method is not reliable at high frequencies because it provides only about half a clock period of setup and hold time in many cases. Fixed-pulse width clock waveforms must be used in designs with multiple frequencies, thus making clock generation and distribution more difficult.
There is clearly a need for a method that allows data signals to be exchanged safely between clock domains of the same or different frequencies, that leads to efficient automation and that can work in the context of high-speed testing of circuits using logic BIST. Such a method must be capable of providing a setup and hold time of more than the one half of one clock period of the highest frequency used for testing provided by the current methods.